Most CPLDs (complex programmable logic devices) use a mode that reduces power consumption, but when the system is not in use, the power should be completely cut off to conserve battery power, thus achieving many designers' ultimate energy saving goals. Figure 1 depicts how to add several discrete components to a CPLD to implement a system power-down circuit that conserves battery power. In this example, the CPLD used is the Altera EPM570-T100. An external P-channel MOSFET Q1 and an International Rectifier's IRLML6302 (or equivalent) form a power control switch for the IC1 CPLD. The CPLD and switch matrix control the gate of the MOSFET. When the user presses a switch, the bias of the switch is applied to Q1. The CPLD has an embedded timer for monitoring the operation of the switch and system. When the system is in a specific out-of-duty cycle, the timer removes the gate drive of the MOSFET, causing the CPLD and other components connected to the MOSFET to be powered down.
The source of Q1 is connected to the positive terminal of the battery, and its drain is connected to the VCC (INT), VCC (IO1), and VCC (IO2) power pins of IC1 and other components that require power-off control. When the power is turned off, a 1kΩ pull-up resistor R3 maintains the gate-source voltage of Q1 at 0V, maintaining its off state. When the IC1 power is turned off, it establishes a ground-to-ground leakage path through the power-down pin of the CPLD. The EPM570T100 features hot-plug protection that limits the I/O pin of any user-accessible device to less than 300mA. Therefore, even in the worst case, the I/O pin voltage generated on R3 does not reach the 0.7V minimum gate threshold turn-on voltage of the FET.
Pressing any switch establishes a current path through the switch contacts and the corresponding diode, thus producing a gate-source bias of approximately 2.3V on R3, which is sufficient to turn Q1 on for approximately 100ms and power IC1 . When the mechanical switches are activated, their minimum on-time is at least 3ms, while a typical operator's push/release time is at least 30ms. Since the response time of the person is relatively slow, the CPLD can complete the on-time, reset the internal circuit, and maintain the power-off pin that turns Q1 on in a logic-zero state before the operator releases the switch.
In addition to the user-set application logic (not shown), CPLD's power control logic adds a pair of standard-parameter library macros, which are generated by Altera's Quartus II development tools. The internal 4.4MHz ± 25% oscillator Altufm_osc drives a modular 44 million LPM (Library Parameterization Module) counter. The logic low level signal generated by the CPLD application logic or when any switch is turned off will reset the counter. When the counter is reset, its execution signal goes low, driving an external power-down pin. When the reset is removed, the inverted execution signal restarts the operation of the LPM counter.
If all switches are on and the application logic is inactive, the counter counts to 44 million in about 10 seconds, then the internal execution signal goes high, turns off the counter, and keeps the execution signal high. Next, the power-off pin climbs to VCC, and turns off Q1 when the power-off pin voltage reaches 2.3V. Turning off the power to the CPLD causes the power-down pin to enter a three-state (or no-connect) mode, while R3 keeps Q1 off.
The user can use the JTAG-compliant command to connect to a factory-defined 10-pin plug with a download cable to configure the EPM570-T100. This process requires an external switch before, during, and after configuration to ensure that the CPLD can receive power during configuration. The non-working time can be set to any desired value by changing the module of the counter. Although the power, ground, and JTAG signals all use dedicated device pins, any general-purpose CPLD I/O pin can be configured as a switch input and a power-down output.
If your application requires a pushbutton switch matrix, you can use n diodes to form an nxm switch for efficient power-up detection (Figure 2). In this example, rows of switches are connected to the gate of the MOSFET through diodes D1~D4. Resistors R8~R11 provide a ground path for each row of switches and carry current only when the switch is closed, allowing the line input to be low while ensuring that only the minimum supply current is consumed.
When the user presses any of the switches, the gate of Q1 is low and the CPLD is turned on. Before the user releases the switch, a fast CPLD power-up routine scans the rows and rows of the switch array to determine which switch the user pressed. And the reset signal resets the inoperative timer of the LPM counter.
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